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100G QSFP Evaluation Board
100G QSFP Evaluation Board
  • 100G QSFP Evaluation Board

100G QSFP Evaluation Board

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InFiberone P/N: GTB-080-V4-01.pcba
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US$2000.00US$2000.00

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100G QSFP Evaluation Board

 

 

Features

  • 16 SMA Connectors for High-Speed Data, up to 28Gbps perlane
  • RJ45 to I2Ccontrolled 
  • 5V powersupply 
  • RoHS 6 compliant (leadfree)

 

Applications


  •        Test and incoming inspection for transceivers, active optical cables and electricloopbacks
  •         Memory map programming for transceivers and electricloopbacks
  •         Transceiver and active optical cable development andanalysis 


 

Description

Infiberone 100G QSFP Host Evaluation Board is designed to provide an efficient and easy method of testing 100G QSFP transceivers, active optical cables, and customizing electric loopbacks.

As there are twohigh-speedsignallinesforeachlane,oneforpositiveandtheotherfornegative, testing in single-ended or differential mode both could be accomplished. The outer conductor inner-diameter of the SMA should be 2.92mm. As for details of electrical connector and cage, refers to agreement SFF-8436please.



There are 6 LED on the Evaluation board to indicate the real time status, separately serve for power supply and five low speeds electrical hardware pins called ModSelL, ResetL, LPMode, ModPrsL and IntL. The ModSelL, LPMode and ResetL pins can be changed to high or low level by hardware directly on the Evaluation board. CDRs are usually integrated into the modules. Via the RJ45 port, software function could be accomplished, using the GUI by computer.

 

Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Unit

Supply Voltage

Vcc

-0.3

3.6

V

Input Voltage

Vin

-0.3

Vcc+0.3

V

Storage Temperature

Tst

-20

85

ºC

Case Operating Temperature

Top

0

70

ºC

Humidity(non-condensing)

Rh

5

95

%

 

 Recommended Operating Conditions

Parameter

Symbol

Min

Typical

Max

Unit

Supply Voltage

Vcc

 

5

 

V

Supply current

ILIMIT

 

 

3

A

Data Rate Per Lane

fd

 

25.78125

40

Gbps

Operating Case temperature

Tca

0

 

70

ºC

Humidity

Rh

5

 

85

%



QSFP Edge Connector and Pinout Description


The electrical interface to the transceiver is a 38-pin edge connector. The 38-pins provide high speed data, low speed monitoring and control signals, I2C communication, power and ground connectivity. The top and bottom views of the connector are provided below, as well as a table outlining the contact numbering, symbol and full description.

Low Speed Electrical Hardware Pins

In addition to the 2-wire serial interface the module has the following low speed pins for control and status:

 

   (1)   ModSelLPin

The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. When the ModSelL is “High”, the module will not respond to any 2-wire interface communication from the host. ModSelL has an internal pull-up in the module.

(2)   ResetLPin

Reset.LP Mode_Reset has an internal pull-up in the module. Alow level on the Reset Lp in for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module will post this completion o freset interrupt without requiring are set.

  (3)   LPMode Pin

The LP Mode pin shall be pulled up to Vcc in the QSFP+ module .WhenLPMode='1',the module power is reduced to below 1.5W.In this state,TWS communication is operational,but the transmitter functionality is disabled. In addition, the LPMode can be controlled by software control bits. The software controlbits



LPMode

Power_Overide Bit

Power_set Bit

Module Power Allowed

1

0

X

Low Power (< 1.5W)

0

0

X

High Power (< 3.5W)

X

1

1

Low Power (< 1.5W)

X

1

0

High Power (< 3.5W)


(4)   ModPrsLPin

ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL is asserted “Low”whenthemoduleisinsertedanddeasserted“High”whenthemoduleisphysicallyabsentfromthe hostconnector.

 

(5)   IntLPin

IntLisanoutputpin.When“Low”,itindicatesapossiblemoduleoperationalfaultorastatuscriticaltothe host system. The host identifies the source of the interrupt by using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled up to Vcc on the hostboard.