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40G QSFP Evaluation Board
40G QSFP Evaluation Board
  • 40G QSFP Evaluation Board

40G QSFP Evaluation Board

40G QSFP Evaluation Board
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InFiberone P/N: GTB-042-V0-01.pcba
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40G QSFP EVALUATION BOARD PN:GTB-042-V0-01.pcba



 Feature:    

·     16 SMA Connectors for High-Speed Data 

·     RJ45 to I2C controlled 

·     Evaluates Data Rates up to 40 Gbps 

·     With TX and RX CDR each lane, up to 11.3Gbps 

·     5V power supply voltage 

·     RoHS 6 compliant (lead free)

 

Application: 

·     Test and incoming inspection for transceivers, active optical cables and electric loopbacks 

·     Memory map programming for transceivers and electric loopbacks 

·     Transceiver and active optical cable development and analysis

 

Description: 

The Infiberone 40G QSFP/QSFP+ Host Evaluation Board is designed to provide an efficient and easy method of testing 40G QSFP/QSFP+ transceivers, active optical cables, and customizing electric loopbacks.

As there are two high-speed signal lines for each lane, one for positive and the other for negative, testing in single-ended or differential mode both could be accomplished. The outer conductor inner-diameter of the SMA should be 3.5mm. As for details of electrical connector and cage, refers to agreement SFF-8436 please.

 

Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Unit

Supply Voltage

Vcc

-0.3

3.6

V

Input Voltage

Vin

-0.3

Vcc+0.3

V

Storage Temperature

Tst

-20

85

ºC

Case Operating Temperature

Top

0

70

ºC

Humidity(non-condensing)

Rh

5

95

%

 

 

Recommended Operating Conditions

Parameter

Symbol

Min

Typical

Max

Unit

Supply Voltage

Vcc

 

5

 

V

Supply current

ILIMIT

 

900

 

mA

Data Rate Per Lane

fd

9.95

10.3125

11.3

Gbps

Operating Case temperature

Tca

0

 

70

ºC

Humidity

Rh

5

 

85

%

QSFP Edge Connector and Pinout Description




The electrical interface to the transceiver is a 38-pin edge connector. The 38-pins provide high speed data, low speed monitoring and control signals, I2C communication, power and ground connectivity. The top and bottom views of the connector are provided below, as well as a table outlining the contact numbering, symbol and full description.

 

 Low Speed Electrical Hardware Pins

In addition to the 2-wire serial interface the module has the following low speed pins for control and status:

 

(1)   ModSelL Pin

The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. When the ModSelL is “High”, the module will not respond to any 2-wire interface communication from the host. ModSelL has an internal pull-up in the module.

 

(2)   ResetL Pin

Reset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module will post this completion of reset interrupt without requiring a reset.


(3)   LPMode Pin

LPMode

Power_Overide Bit

Power_set Bit

Module Power Allowed

1

0

X

Low Power (< 1.5W)

0

0

X

High Power (< 3.5W)

X

1

1

Low Power (< 1.5W)

X

1

0

High Power (< 3.5W)


The LPMode pin shall be pulled up to Vcc in the QSFP+ module. When LPMode='1', the module power is reduced to below 1.5W. In this state, TWS communication is operational, but the transmitter functionality is disabled. In addition, the LPMode can be controlled by software control bits. The software control bits are Power_over-ride and Power_set located in page LOWER MEMORY, Address byte 93 bits 0, 1 as shown in table below.

(4)   ModPrsL Pin

ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL is asserted “Low” when the module is inserted and deasserted “High” when the module is physically absent from the host connector.

 (5)   IntL Pin

IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt by using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled up to Vcc on the host board.

 

Recommended Host Board Power Supply Filtering


Ordering information

Part Number

Product Description

 

GTB-042-V0-01.pcba

 

40G QSFP Evaluation Board, with CDR in each lane

 

References

1.   SFF-8436 QSFP+

2.   Ethernet 40GBASE

 

Important Notice

Performance figures, data and any illustrative material provided in this data sheet are typical and must be specifically confirmed in writing by INFIBERONE before they become applicable to any particular order or contract. In accordance with the INFIBERONE policy of continuous improvement specifications may change without notice.

The publication of information in this data sheet does not imply freedom from patent or other protective rights of INFIBERONE or others. Further details are available from any INFIBERONE sales representative.